1. Field of the Invention
The present invention relates in general to a clock control circuit for a Rambus dynamic random access memory (DRAM). More particularly, it provides an improved clock control circuit for a Rambus DRAM which reduces power consumption by generating a clock signal for externally outputting an internal data only in a read or current control command.
2. Description of Related Art
In general, a Rambus DRAM is a packet driving memory device for transmitting packet type data and control signals. A plurality of Rambus DRAMs are connected on a Rambus channel. Each Rambus DRAM is controlled by a Rambus memory controller through the Rambus channel.
A command packet in the Rambus DRAM is divided into a primary control packet(PCP) and a secondary control packet(SCP). The SCP includes various commands such as a read command and a current control command. When the read or current control command is applied to the Rambus DRAM, an internal clock signal tclk is enabled and used to externally output an internal data.
Conventionally, whenever the SCP is applied, the clock signal tclk is enabled. When it is judged by command decoding that an applied command signal is not a read or current control command, the clock signal tclk is disabled. If the command signal is the read or current control command, the clock signal tclk is maintained as it is. Accordingly, a large volume of SCPs are applied, and many unnecessary clock signals are generated when the SCP command is not a read or current control command. These unnecessary clock signals cause wasted power consumption. The operation and disadvantages of a conventional clock control circuit will now be explained with reference to the accompanying drawings.
As illustrated in FIG. 1 (Prior Art) and FIG. 2 (Prior Art), the SCP type in the command application method for the Rambus DRAM is divided into a COLC packet (FIG. 1) and a COLX packet (FIG. 2).
As shown therein, the SCP is synchronized with a CFM clock, and thus the command is applied consecutively through five pins COL0, COL1, . . . , COL4.
In the COLC packet (FIG. 1), DC[4:0] denotes a device address where the command will be performed, and COP[3:0] denotes a command OP_code(here, OP_code implies a command code performed by a device). In addition, BC[3:0] denotes a bank address, and C[5:0] denotes a column address.
In the COLX packet (FIG. 2), DX[4:0] denotes a device address, and XOP[4:0] denotes a command OP_code. BX[3:0] denotes a bank address.
According to COP[3:0] of the COLC packet, various commands including the read, write and precharge operations can be performed. According to XOP[4:0] of the COLX packet, the current control and precharge operations can be performed.
The COLC packet and the COLX packet can be combined and applied at the same time. In this case, the SCP can simultaneously apply a command to two devices.
FIG. 3 (Prior Art) is a schematic diagram of a conventional circuit for generating a clock enable signal tclk_en, which, in turn, generates the clock signal tclk. An input signal detecting unit 10 receives a signal idhit_cas_ffl indicating whether a value of DC[4:0] is identical to its address and a signal idhit_cas_othr indicating whether a value of DX[4:0] is identical to its device address, and for enabling an output signal etck_en when at least one signal is enabled. An output signal maintaining unit 20 generates a control signal ten_in1_b for maintaining an enable state of the clock enable signal tclk_en outputted in the read or current control command. An output signal control unit 30 receives the output signal etck_en from the input signal detecting unit 10, and generates a control signal ten_in2_b for disabling the output signal tclk_en when the command is not the read or current control command. A signal generating unit 40 receives the signal idhit_cas_ffl, the signal idhit_cas_othr, the output signal ten_in1_b from the input signal detecting unit 20, and the output signal ten_in2_b from the output signal control unit 30, and generates the clock enable signal tclk_en.
When the command is applied with the SCP command packet on a Rambus DRAM module (maximally 32 devices), the respective Rambus DRAMs on the module compare DC[4:0] and DX[4:0] with their device addresses. Each Rambus DRAM converts the signal idhit_cas_ffl to a high level when the value of DC[4:0] is identical to their device addresses, and converts the signal idhit_cas_othr to a high level when the value of DX[4:0] is identical to their device addresses.
In the conventional circuit for generating the clock enable signal tclk_en, when one of the signals idhit_cas_ffl, idhit_cas_othr is at a high level, the output signal tclk_en from a NAND gate NA3 of the signal generating unit 40 becomes a high level, thereby generating the clock signal tclk. In addition, the output signal etck_en from a NAND gate NA1 of the input signal detecting unit 10 also becomes a high level, and thus an enable terminal EN of a flip-flop FF4 which is a latch circuit becomes a high level. Accordingly, the output signal ten_in2_b from a flip-flop FF4 is at a low level. Therefore, if not set through a set terminal S(Q=1), the output signal tclk_en from the NAND gate NA3 is maintained at a high level.
When the output signal ten_in1_b from the output signal maintaining unit 20 generated due to a special command(not the read or current control command) is at a high level, the output signal ten_in2_b from the flip-flop FF4 of the output signal control unit 30 is set after three cycles(the signal etck_en is consecutively transmitted, and thus the signal etck_en_rst becomes xe2x80x981xe2x80x99), thereby converting a high value of the clock enable signal tclk_en to a low level.
That is, when a sequence of applying a command to one of the 32 devices on the module with one of the COLC and COLX packets is consecutively carried out, toggling of the unnecessary clock signal tclk occurs in three cycles in the device identical to the device address value of the other packet(value of DC[4:0] of the COLC packet or DX[4:0] of the COLX packet).
For example, when the 32 Rambus DRAMs are on the module, if the read command(COP=0011) is externally applied to the 10th device (DC=01010) with the COLC packet, the value of the COPX packet is generally xe2x80x98DX=00000xe2x80x99 and xe2x80x98XOP=00000xe2x80x99. In this case, since the value of DX is xe2x80x980xe2x80x99, the signal idhit_cas_othr informing that the device ID is matched in the 0th device becomes a high level. Accordingly, toggling of the clock signal tclk occurs in the 0th device as well as the 10th device. Thereafter, since the value of XOP is xe2x80x980xe2x80x99, the clock signal tclk is disabled after three cycles.
FIG. 4 (Prior Art) shows an operation timing of a COL packet of the Rambus DRAM. When the signal idhit_cas_othr(h) becomes a high level by applying the command with the COLX packet, the clock enable signal tclk_en(d) becomes a high level, and thus a clock signal tclka(e) and a clock signal tclkb(f) are operated, thereby generating a pulse. However, when it is judged that the command is not the read or current control command, the clock enable signal tclk_en(d) is disabled after three cycles, thereby controlling generation of the clock signals tclka, tclkb(e)(f).
In the conventional Rambus DRAM, when the SCP command is applied, the internal clock enable signal tclk_en becomes a high level, and thus the clock signal tclk is enabled. Thereafter, according to the command analysis, if the applied command is not the read or current control command, the clock enable signal tclk_en is disabled after three cycles. As a result, toggling of the clock signal tclk unnecessarily occurs in the three cycles, which results in large power consumption.
The present invention provides a clock control circuit for a Rambus DRAM which reduces power consumption by judging in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only if the applied command is a read or current control command.
An input signal detecting unit generates an enable signal when one a first and second comparing signals is enabled. The first comparing signal compares an address value of the selected Rambus DRAM with an applied device address value of a COLC packet. The second comparing signal compares the address value of the selected Rambus DRAM with an applied device address value of a COLX packet. When the applied command is a read or current control command, the command is applied with an SCP command packet on a Rambus DRAM module. A signal generating unit generates a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled. An output signal maintaining unit outputs to the signal generating unit a control signal for maintaining the clock enable signal from the signal generating unit in the read or current control command. An output signal control unit outputs to the signal generating unit a control signal for controlling generation of the clock enable signal from the signal generating unit, when the command applied according to the enable signal outputted from the input signal detecting unit is not the read or current control command.
The input signal detecting unit includes: a first NAND gate for receiving a COP[1] signal(rqin2 less than 1 greater than signal) which is a bit implying the read or current control command in COP[3:0] which is an op_code of the COLC packet, and the first comparing signal; a second NAND gate for receiving a COP[1] signal(rqin3 less than 3 greater than signal) which is a bit implying the read or current control command in COP[3:0] which is an op_code of the COLX packet, and the second comparing signal; and an OR gate for receiving an inverted signal of the output signal from the first NAND gate and an inverted signal of the output signal from the second NAND gate.
The output signal control unit includes: a first flip-flop for receiving the enable signal from the input signal detecting unit as an input signal, and a clock signal as a clock input; a second flip-flop for receiving an inverted signal of the output signal from the first flip-flop as an input signal, and the clock signal as a clock input; a third flip-flop for receiving the output signal from the second flip-flop as an input signal, and the clock signal as a clock input; an OR gate for receiving an inverted signal of the output signal from the third flip-flop and an inverted signal of a reset bar signal; and a fourth flip-flop for receiving the output signal from the input signal detecting unit as an enable signal, the output signal from the OR gate as a set signal, and a ground voltage as an input signal, and outputting an output signal to the signal generating unit.
The signal generating unit includes: an OR gate for receiving an inverted signal of the first comparing signal, an inverted signal of the second comparing signal, an inverted signal of the output signal from the output signal control unit, and an inverted signal of the output signal from the output signal maintaining unit, and for generating the clock enable signal tclk_en.